Samuel Garcia

Maître de conférences
Site web :

2022

Articles de conférence

  1. Zhang, M. J.; Garcia, S. and Terre, M. Fast Learning Architecture for Neural Networks. In 2022 30th European Signal Processing Conference (EUSIPCO), pages 1611-1615, IEEE, Belgrade, Serbia, 2022. doi  www 
  1. Merhej, D.; Ahriz, I.; Garcia, S. and Terre, M. LoRa Based Indoor Localization. In 2022 IEEE 95th Vehicular Technology Conference (VTC2022-Spring), pages 1-5, IEEE, Helsinki, France, 2022. doi  www 

2014

Articles de conférence

  1. Wassi, G.; Benkhelifa, M. El A.; Lawday, G.; Verdier, F. c. and Garcia, S. Multi-shape Tasks Scheduling for Online Multitasking on FPGAs. In International Symposium on Reconfigurable Communication-centric Systems_on-Chip (ReCoSoC'2014), pages 1-7, Montpellier, France, 2014. doi  www 

2011

Articles de conférence

  1. Garcia, S. and Granado, B. Task model and online operating system API for hardware tasks in OLLAF platform. In Workshop on Design and Architectures for Signal end Image Processing, pages 1-7, Finland, 2011. www 

2008

Articles de conférence

  1. Garcia, S. and Granado, B. OLLAF : a Dual Plane Reconfigurable Architecture for OS Support. In International Design and Test Workshop, pages 282-287, Tunisia, 2008. www 
  1. Garcia, S. and Granado, B. OLLAF : a Fine Grained Dynamically Reconfigurable Architecture for OS Support. In Workshop on Design and Architectures for Signal end Image Processing, pages 1, Belgium, 2008. www 
  1. Garcia, S. and Granado, B. Design of a Fine Grained Dynamically Reconfigurable Architecture for OS Support. In Conferance on Design of Circuits and Integrated Systems, pages 32, Grenoble, France, 2008. www 

2007

Articles de conférence

  1. Garcia, S.; Prévotet, J-C. and Granado, B. Hardware task context management for fine grained dynamically recon gurable architecture. In Workshop on Design and Architectures for Signal and Image Processing, pages 1, Grenoble, France, 2007. www 
  1. Garcia, S.; Prévotet, J.-C. and Granado, B. Hardware task context management for fine grained dynamically reconfigurable architecture. In Workshop on Design and Architectures for Signal and Image Processing, Unknown, Unknown Region, 2007. www 
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