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[HM09a] Timed SystemC Waiting State Automata
Conférence Internationale avec comité de lecture : On the Third International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS), July 2009, pp.60-72, Rabat, Morroco, (DOI: http://hal.archives-ouvertes.fr/hal-00672908/)Mots clés: SystemC, time analysis, compositional veriï¬cation, automata, model-checking
Résumé:
System-Level Modeling using system-level languages like SystemC or SystemVerilog
is gaining more and more popularity. They are supposed to provide the garantee
of critical functional properties about the interaction between concurrent processes
like determinism or liveness up to a basic unit, the delta-cycle. Additionnally
to this functional correctness, system level models should also provide valuable
information about important non-functional properties like time constraints. Since
timing properties (execution times, delays, periods, etc.) are especially important
in performance veriï¬cation of multiprocessing real-time embedded systems, we
propose a formal model based on SystemC waiting-state automata that conforms
to the SystemC scheduler up to delta-cycles (1) and that also conforms to the provided
time constraints (2).
Equipe:
sys
BibTeX
| @inproceedings { | |||
| HM09a, | |||
| title | = | "{Timed SystemC Waiting State Automata}", | |
| author | = | " N. Harrath and B. Monsuez ", | |
| booktitle | = | "{On the Third International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS)}", | |
| year | = | 2009, | |
| month | = | "July", | |
| pages | = | "60-72", | |
| address | = | "Rabat, Morroco", | |
| doi | = | "http://hal.archives-ouvertes.fr/hal-00672908/", | |
| } | |||
