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[DMH11] Building SystemC waiting state automata
Conférence Internationale avec comité de lecture : Fifth International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2011), July 2011, pp.54-66,Mots clés: SystemC, Automata, opertionl semantics, symbolic execution, compositional verification SystemC, Automata, opertionl semantics, symbolic execution, compositional verification SystemC, Automata, opertionl semantics, symbolic execution, compositional verification
Résumé:
SystemC is becoming a de facto standard for the system-level
description of system-on-chip. However most formal verification
techniques used for verifying hardware components targets low level
design, usually netlist or RTL, but time-to-market requirements have
rushed the industry towards design paradigms that offer a very high
level of abstraction. In previous works, we proposed a verification
methodology based on SystemC waiting-state automata, an abstract
formal model for verifying properties of SystemC at the transaction
level within a delta-cycle. The main drawback of thismodel is that it
should be providedmanually. In this paper, we propose a method to
automatically build the SystemC waiting-state automata from the
SystemC code. It is based on an extended symbolic execution of the
SystemC design that takes care of synchronous as well as asynchronous
communications and that preserves the semantics of SystemC up to a
delta-cycle
Equipe:
sys
BibTeX
| @inproceedings { | |||
| DMH11, | |||
| title | = | "{Building SystemC waiting state automata }", | |
| author | = | " J. Delacroix and B. Monsuez and N. Harrath ", | |
| booktitle | = | "{Fifth International Workshop on Verification and Evaluation of Computer and Communication Systems (VECoS 2011)}", | |
| year | = | 2011, | |
| month | = | "July", | |
| pages | = | "54-66", | |
| } | |||
